1. Field of the Invention
The present invention relates to an internal voltage generator installed within a semiconductor memory device, and more particularly, to an internal voltage generator that prevents a center value in a Gaussian distribution of a produced internal voltage from largely moving even when a process parameter severely deviates during the manufacture of a semiconductor memory device, that reduces a setup time for an internal voltage, and that minimizes power consumption, thereby improving the yield.
2. Description of the Related Art
Semiconductor memory devices employ not only an external high supply voltage and an external low supply voltage, of which a ground voltage is representative, but also generate and utilize an internal voltage having a voltage level between the high and low supply voltages the parameters of which are determined in consideration of consumed power and device operating speed.
FIG. 1 is a circuit diagram of a conventional internal voltage generator 100. Referring to FIG. 1, the internal voltage generator 100 includes a reference voltage generation block 110, a comparator block 120, and an output driving block 130.
The reference voltage generation block 110 includes a plurality of resistors R1, R2, and R3 serially connected to each other between a high supply voltage VDD and a low supply voltage GND. The reference voltage generation block 110 selects two voltage drop values among the resistors R1, R2, and R3 and outputs the selected two voltages as a first reference voltage VL and a second reference voltage VH. The first reference voltage VL has a voltage level that is lower than the level of the second reference voltage VH.
The comparator block 120 includes two comparators, namely, a first comparator 121 and a second comparator 122. The first reference voltage VL is applied to a negative input port (−) of the first comparator 121, and an internal voltage VCNT is applied to a positive input port (+) thereof. The internal voltage VCNT is a final voltage level that is generated by the internal voltage generator 100. The second reference voltage VH is applied to a negative input port (−) of the second comparator 122, and the internal voltage VCNT is applied to a positive input port (+) thereof. The first comparator 121 compares the first reference voltage VL with the internal voltage VCNT and outputs a first comparison voltage UPB as a result of the comparison. The second comparator 122 compares the second reference voltage VH with the internal voltage VCNT and outputs a second comparison voltage DN as a result of the comparison. The first and second comparators are open-loop-configured operational amplifiers.
The output driving block 130 includes a P-type MOS transistor MP1, an N-type MOS transistor MN1, and a capacitor C. The P-type MOS transistor MP1 has one end connected to a high supply voltage VDD and a gate to which the first comparison voltage UPB is applied. The N-type MOS transistor MN1 has one end connected to a low supply voltage GND and a gate to which the second comparison voltage DN is applied. The capacitor C has one end connected to a low supply voltage GND and the other end connected to both the other end of the P-type MOS transistor MP1 and the other end of the N-type MOS transistor MN1.
When the P-type MOS transistor MP1 is turned on, current flowing from the high supply voltage VDD is stored in the form of charge in the capacitor C. When the N-type MOS transistor MN1 is turned on, the charge stored in the capacitor C is discharged to a low supply voltage GND. A voltage level of a voltage drop in the capacitor C is equal to the high supply voltage VDD when charge has been stored in the capacitor C, and is equal to the low supply voltage GND when charge has been discharged from the capacitor C.
In an operation of the conventional internal voltage generator 100 of FIG. 1, currents IUP and IDN flowing in the two MOS transistors MP1 and MN1 are controlled in response to the two comparison voltages UPB and DN produced by the two reference voltages VL and VH and the internal voltage VCNT. The level of the internal voltage VCNT depends upon the amounts of current flowing in the two MOS transistors MP1 and MN1. An internal voltage VCNT having a predetermined level is fed back to the comparator block 120 and changes the voltage levels of the comparison voltages UPB and DN of the first and second comparators 121 and 122. The internal voltage VCNT has a final voltage level that is between the two reference voltages VL and VH (i.e., VL<VCNT<VH). The time period that lapses from the time when a power supply is being applied to a time when a level of the internal voltage VCNT reaches a predetermined voltage level is referred to as a setup time.
When the two MOS transistors MP1 and MN1 of the output driving block 130 are simultaneously turned on, a direct path of current flows between the high supply voltage VDD and the low supply voltage GND. The direct path of current is not necessary and causes a waste of power. Accordingly, to prevent the two MOS transistors MP1 and MN1 from being simultaneously turned on, a voltage difference between the two reference voltages VL and VH, that is, an offset section OFFSET, is increased.
FIG. 2 is a graph showing a relationship among a plurality of internal voltages within the voltage generator 100. Referring to FIG. 2, an area between the two reference voltages VL and VH is referred to as an offset section VOFFSET, and a hatched area of the offset section VOFFSET where the two MOS transistors MP1 and MN1 are simultaneously turned off is referred to as a dead zone VDZ. In the dead zone VDZ, a direct path current flows from a high supply voltage VDD to a low supply voltage GND, and the internal voltage VCNT is not accurately adjusted. Hence, it is preferable that the dead zone VDZ is narrow. Considering that gains of the first and second comparators 121 and 122 are not infinite, it is evident that the dead zone VDZ is narrower than the offset section VOFFSET. In FIG. 2, VTP denotes a threshold voltage of the first MOS transistor MP1, and VTN denotes a threshold voltage of the second MOS transistor MN1.
FIG. 3 is a graph showing a relationship among a plurality of voltages within the internal voltage generator 100 that are affected by an offset error and a gain error made by the comparators constituting the comparator block 120 of FIG. 1.
Referring to FIG. 3, even when the first and second comparators 121 and 122 have offset voltages of opposite polarities, the two MOS transistors MP1 and MN1 are simultaneously turned on, so that a direct path current may flow between a high supply voltage VDD and a low supply voltage GND. A dotted characteristic curve indicates a case where no offset is generated, and a solid characteristic curve indicates a case where an offset has been generated.
To overcome an offset error and a gain error of the comparators 121 and 122 generated due to a deviation occurring in the manufacture of a semiconductor memory device, the offset section VOFFSET should be made wider. Furthermore, the two reference voltages VL and VH determined by the serially connected resistors R1, R2, and R3 are greatly affected by the process deviation. Accordingly, the offset section VOFFSET must be widened even further to improve the yield of a semiconductor device.
However, the widening of the offset section VOFFSET to improve the yield of a semiconductor device and to overcome offset and gain errors can lead to the following problems. First, the dead zone VDZ increases with an increase of the offset section VOFFSET.
Second, an intermediate value of a wide offset section VOFFSET, which is used as a voltage level of the internal voltage VCNT, can change according to the accuracy of a process, so it is not easy to produce an internal voltage VCNT having a designated voltage level.
The internal voltage generator 100 of FIG. 1 also has another problem, in the form of setup time. When receiving initial power, the internal voltage generator 100 should produce an internal voltage VCNT within a short period of time. A determination of whether the internal voltage VCNT has been produced within a short period of time is made based on the setup time.
When there is a significant difference between a voltage level of the internal voltage VCNT biased when an initial supply voltage is supplied to the internal voltage generator 100 and a desired voltage level of the internal voltage VCNT, the internal voltage VCNT can be produced within a shorter period of time as more current is supplied or discharged by the P-type and N-type MOS transistors MP1 and MN1. However, since the sizes of the two MOS transistors MP1 and MN1 are set during manufacturing, the amount of current that flows cannot be arbitrarily controlled.